TSV 3D integration technology is based on through-silicon interconnect technology (Through-Silicon-Via, TSV for short) and chip-stack technology (System-In-Package, SIP for short), interconnected at the chip level through TSV Realize vertical integration and communication between homogenous or heterogeneous chips; compared with traditional SIP technology, it has the advantages of short interconnect length, low latency, high bandwidth, high integration density, small size and low power consumption.

High aspect ratio TSV copper plating filling structure

Maximum aspect ratio of 10, minimum diameter of 10μm, maximum depth of 400μm

(a)through hole

(b)blind hole

TSV structure

The annular TSV has a hollow structure, which is favorable for stress release and reduces packaging;
Compared to all-copper-filled TSV, the ring-shaped TSV has better RF performance and lower
 high-frequency loss.

Air insulated low resistance silicon TSV structure

A low stress package is achieved by releasing the stress generated by the temperature change at the free end. Single TSV resistivity <1.5Ω

Glass-insulated low-resistance silicon TSI structure with pit cavity

There is a cavity structure in communication with the TSI, which is easier to locate for the small chip, and the vertical interconnection length is shorter, avoiding the manufacture of the large aspect ratio TSI;

At the same time, the package volume is reduced

Large size, high aspect ratio, glass-insulated low-resistance silicon TSI structure

Filled with glass paste as insulation, with good insulation and biocompatibility